Area-time optimal adder with relative placement generator
نویسندگان
چکیده
Aamir A. Farooqui , Vojin G. Oklobdzija , Sadiq M. Sait Synopsys Inc. Synopsys Module Compiler 700 Middlefield Road, Mountain View CA 94043 USA [email protected] ACSEL Laboratory Electrical Engineering Dept. University of California Davis, CA 95616 USA [email protected] 3 Department of Computer Engineering KFUPM Box 673 King Fahd University of Petroleum & Minerals Dhahran-31261, Saudi Arabia [email protected]
منابع مشابه
TO APPEAR IN : IEEE TRANSACTIONS ON CAD / ICAS 1 On the Generation of Area - Time OptimalTestable
| We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition tn and the fault model FM. FM may in particular be chosen as the classical stuck-at fault model, the cellular fault model or the robust path delay fault model. The output of the generator is a performanc...
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